The applicant of the present invention proposes in Japanese Patent Laid-Open Publication No. 6-168349 a usable multiplication circuit for the above field, which realizes multiplication of an analog voltage and a digital multiplier without analog-to-digital (A/D) conversion.
FIG. 9 shows a conventional circuit. Input voltage X is input to capacitive coupling CP including capacitances CC0 to CC8 through switches SW1 to SW8. The output of CP is input to inverting amplifying circuit INV2, whose output is connected to its input through feedback capacitance C3.
CP outputs the result of multiplication and addition operation for X wherein multiplication is done by multiplying X by a weight which is proportional to each capacitance, and INV2 transmits the outputs to the next stage with good linearity due to the large gain and the feedback system of C3. As each capacitance of CP corresponds to each binary bit, multiplication with binary numbers can be performed by controlling the opening and closing of each switch.
Through intermediate capacitance C4, the output of INV2 is connected to inverting amplifying circuit INV3, whose input and output are connected through feedback capacitance C5. The output of CP is transmitted to the two successive stages to obtain a non-inverted output.
In CP, capacitance CC8 is also connected in parallel to the other capacitances. CC8 is connected to X through switch SW9, inverting amplifying circuit INV1 and capacitance C1, sequentially. The input and output of INV1 are connected through feedback capacitance C2. When switch SW9 is closed, inverted X (-X) is output with good linearity.